1. Field of the Invention
The present invention relates to Compact Peripheral Component Interconnect (xe2x80x9cCPCIxe2x80x9d) computer systems. More particularly, the present invention relates to providing reliable power redundancy in a CPCI computer architecture.
2. Description of Related Art
CPCI is a high performance industrial bus based on the standard PCI electrical specification in rugged 3U or 6U Eurocard packaging. CPCI is intended for application in telecommunications, computer telephony, real-time machine control, industrial automation, real-time data acquisition, instrumentation, military systems or any other application requiring high speed computing, modular and robust packaging design, and long term manufacturer support. Because of its extremely high speed and bandwidth, the CPCI bus is particularly well suited for many high-speed data communication applications such as servers, routers, converters, and switches.
Compared to standard desktop PCI, CPCI supports twice as many PCI slots (8 versus 4) and offers a packaging scheme that is much better suited for use in industrial applications. Conventional CPCI cards are designed for front loading and removal from a card cage. The cards are firmly held in position by their connector, card guides on both sides, and a faceplate that solidly screws into the card cage. Cards are mounted vertically allowing for natural or forced air convection for cooling. Also, the pin-and-socket connector of the CPCI card is significantly more reliable and has better shock and vibration characteristics than the card edge connector of the standard PCI cards.
Conventional CPCI defines a backplane environment that is limited to eight slots. More specifically, the bus segment of the conventional CPCI system is limited to eight slots, which includes a system slot and peripheral slots. The system slot provides the clocking, arbitration, configuration, and interrupt processing for up to seven peripheral slots.
As is commonly practiced in the art, redundant power is often provided to conventional CPCI computer systems in order to provide stability in the event of power failure. In particular, it has become common in the art to provide redundant power to CPCI backplanes in the form of a secondary power supply. Within these CPCI systems, the primary and secondary power supplies both deliver power to a local power rail on the CPCI backplane. As a result, the CPCI backplane is always provided with power from one power supply in the event of a power failure in the other.
In order to accommodate systems using multiple backplanes, additional power supplies are ordinarily included in the art. In particular, the addition of a second backplane typically requires the addition of a second set of two power supplies. Similar to the aforementioned single-backplane architecture, a dual-backplane architecture routs redundant power to the first backplane by delivering power to the local power rail of the first backplane directly from the first set of two power supplies. Redundant power is then also routed to the second backplane by delivering power to the local power rail of the second backplane directly from the second set of two power supplies. As a result, both backplanes are provided with power stability whenever a single power supply fails within this architecture.
A drawback of this architecture is that it cannot support the emergence of more sophisticated backplanes requiring an increasing amount of power. In particular, the dual-backplane architecture described above is limited in that the power available to either backplane is cut in half whenever one of its respective power supplies fails. As a result, backplanes requiring additional power (i.e., more than a single power supply) do not have sufficient power within this type of architecture.
Accordingly, it would be advantageous to implement an architecture in which additional power, taken from any power supply connected to the CPCI system, is available to any of its backplanes.
The present invention relates to a system and apparatus for distributing power in a compact peripheral component interconnect (CPCI) computer architecture. More specifically, a CPCI computer architecture comprises a plurality of CPCI systems each having respective backplanes. The backplanes further having respective local power rails providing power for a corresponding one of the plurality of CPCI systems. A power distribution system provides power to the backplanes, and comprises a common power rail connected to each one of the local power rails of the backplanes. A plurality of power supplies is connected to the common power rail of the power distribution system. Power taken from any one of the plurality of power supplies is available to any one of the backplanes.
A more complete understanding of a system and apparatus for distributing power in CPCI computer systems will be afforded to those skilled in the art, as well as a realization of additional advantages and objects thereof, by a consideration of the following detailed description of the preferred embodiment. Reference will be made to the appended sheets of drawings which will first be described briefly.